1. Field of the invention
The present invention relates in general to fully-interconnected asynchronous transfer mode (referred to hereinafter as ATM) switching apparatus, and more particularly to a fully-interconnected ATM switching apparatus for providing individual interconnections between all input ports and all output ports and processing a burst traffic by performing two-stage buffering, speed gain control, buffer flow control and statistical multiplexing operations.
2. Description of the Prior Art
The users have required various services of good quality according to the growth of communication techniques. In order to fulfill the requirements of the users, an ATM broadband integrated service digital network (B-ISDN) has been proposed to provide a consecutive service such as a voice service, a high-speed data service such as a file transmission service and a burst data service such as a variable bit rate (VBR) real-time video service on the same transmission link. Under such an environment, multiplexing and switching processing means is the kernel of a communication system and it does not require a time division multiplexing (TDM) method based on a synchronous transfer mode (STM) but a fixed length cell switching method based on an ATM. A construction for embodying such a switching method is shown in FIG. 1.
FIG. 1 is a block diagram illustrating the general construction of a switching apparatus. As shown in this drawing, the switching apparatus comprises a plurality of subdivided line interface circuits 1, a switching function unit 2 and a system manager 3.
Each line interface circuit 1 includes means for performing an interfacing operation to a unit transmission frame. The input line interface circuit 1 performs clock recovery from received signal clock restoration, cell recovery and cell processing operations and then applies a cell destination information (routing tag) to the switching function unit 2 on the basis of a connection identifier and the associated information which is written in a table manager. The switching function unit 2 routs a cell to the associated destination in response to the cell destination information from the input line interface 1. The output line interface circuit 1 receives the cell routed from the switching function unit 2 and changes a channel identifier in the received cell. Then, the output line interface circuit 1 transmits the resultant cell to a subscriber line. In this manner, the cell switching operation is performed.
Constructions of such a switching apparatus are generally classified into the shared memory type, shared bus type, space division type and fully-interconnected type according to embodied architectures. Such switching constructions have their inherent advantages and disadvantages such as cell delay, cell loss, interconnection network complexity, scale extensibility and implementation complexity. For this reason, it is important that the switching apparatus has an optimized construction according to its application and position.
A space division switch such as the Batcher Banyan switch is desirable to readily provide the scale extensibility and reduce the number of interconnections, but has a disadvantage in that it can not provide individual interconnections of one input port to all output ports. For this reason, it is impossible to avoid a cell collision in the switching network. Such an internal blocking phenomenon results in a reduction in performance.
Many efforts such as increasing the number of internal interconnections or the internal processing speed have been made to overcome the above problem with the space division switch. However, such efforts make the switch construction more complex. Noticeably, the number of interconnections is an important factor in the large scale switching construction but it is not an obstacle to an ATM local area network (referred to hereinafter as LAN) hub switch and a small scale ATM switch for a private campus network. Also, switches require a point-to-multipoint switching function for the provision of a multicasting service as well as a simple point-to-point switching function.
Many fully-interconnected switches have been used. The fully-interconnected switches have excellent performance because they can perform a multicasting function without cell copy function. Examples of the fully-interconnected switches will hereinafter be described with reference to FIGS. 2A to 2D.
FIG. 2A is a block diagram illustrating the construction of a conventional cell switching apparatus of the output buffer type employing broadcasting dedicated buses. As shown in this drawing, each of the line interface circuits LI comprises an input driver which is fully coupled to all switch output function units SOFU through an input connector and a broadcasting dedicated bus. Each of the switch output function units SOFU is connected one-to-one to an output driver of each of the line interface circuits LI.
In the case where the system has N input connectors, each switch output function unit SOFU is basically provided with an N-input/l-output multiplexer for receiving the maximum N ATM information cells at a time and outputting the received cells one by one according to an internal service manner.
Each switch output function unit SOFU compares a destination address of the information cell received through the input bus with an inherent address thereof. If the two addresses are the same as a result of the comparison, the switch output function unit SOFU accepts the received information cell. However, in the case where the two addresses are not the same as a result of the comparison, the switch output function unit SOFU discards the received information cell.
The representative switches with the above-mentioned construction are shown in FIGS. 2B to 2D.
FIG. 2B is a block diagram illustrating the construction of a knockout switch employing a knockout concentrator, which is disclosed in U.S. Pat. No. 4,754,451. In the knockout switch, the output addresses of input cells to be routed are classified according to log.sub.2 N bits. Also, the input driver of the line interface circuit LI previously translates an output channel identifier. For this reason, separate function circuits must be added in performing the multicasting switching operation. Further, although the output shared buffer has a redundancy, a cell loss is inevitable when an output cell collision occurs. As a result, the performance may significantly be reduced in the case where a burst traffic is applied.
FIG. 2C is a block diagram illustrating the construction of a switch routing module (SRM) of a multi-stage self-routing switch (MSSR), proposed by Fujitsu in Japan. A VCI controller (VCC) at the input stage of the line interface circuit LI analyzes an input cell and outputs cell data with desired output routing information and a translated channel identifier in accordance with the analyzed result. As a result, copied cells cannot have different channel identifiers for the multicasting operation. Also, switch output buffers are multiplexed in a simple hub-polling mechanism manner at the same speed as that of the output driver of the line interface circuit LI, resulting in a reduction in performance in the case where a burst traffic is applied.
FIG. 2D is a block diagram illustrating the construction of a cylinder switch, proposed by Colombia University in U.S.A. The cylinder switch employs ring buffer multiplexing means. For this reason, the cylinder switch has a complex slotted ring mechanism and priority control and cell order maintenance functions for the output control, resulting in a complexity in construction. Also, additional bytes must be appended to cell data to perform such control functions. As a result, the transmission efficiency may be reduced.